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1-to-1 differential- to-lvcmos/lvttl translator ICS83021I idt? / ics? lvcmos/lvttl translator 1 ics83031ami rev. c october 31, 2008 general description the ICS83021I is a 1-to-1 differential-to-lvcmos/ lvttl translator and a member of the hiperclocks? family of high performance clock solutions from idt. the differential input is highly flexible and can accept the following input types: lvpecl, lvds, lvhstl, sstl, and hcsl. the small 8-lead soic footprint makes this device ideal for use in applications with limited board space. features ? one lvcmos/lvttl output ? differential clk/nclk input pair ? clk/nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency: 350mhz (typical) ? part-to-part skew: 500ps (maximum) ? additive phase jitter, rms: 0.21ps (typical), 3.3v output ? full 3.3v and 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 1 2 3 4 8 7 6 5 v dd q0 nc gnd nc nclk nc clk q0 clk nclk pulldown pullup ICS83021I 8-lead soic, 150mil 3.9mm x 4.9mm x 1.375mm package body m package top view pin assignment block diagram
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 2 ics83031ami rev. c october 31, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 4, 6 nc unused no connect. 2 clk input pulldown non-inverting differential clock input. 3 nclk input pullup inverting differential clock input. 5 gnd power power supply ground. 7 q0 output single-ended clock output. lvcmos/lvttl interface levels. 8v dd power positive supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance v dd = 3.6v 23 pf r out output impedance 5 7 12 ?
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 3 ics83031ami rev. c october 31, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v 0.3v or 2.5v 5%, t a = -40c to 85c table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v 0.3v or 2.5v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v dd /2. see parameter measurement information, output load test circuit diagrams. table 3c. differential dc characteristics, v dd = 3.3v 0.3v or 2.5v 5%, t a = -40c to 85c note 1: for single ended applications, the maximum input voltage for clk, nclk is v dd + 0.3v. note 2: common mode voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 103 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.0 3.3 3.6 v 2.375 2.5 2.625 v i dd power supply current 20 ma symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v dd = 3.6v 2.6 v v dd = 2.625v 1.8 v v ol output low voltage; note 1 v dd = 3.6v or 2.625v 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current nclk v in = v dd = 3.6v or 2.625v 5 a clk v in = v dd = 3.6v or 2.625v 150 a i il input low cureent nclk v in = 0v, v dd = 3.6v or 2.625v -150 a clk v in = 0v, v dd = 3.6v or 2.625v -5 a v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 4 ics83031ami rev. c october 31, 2008 ac electrical characteristics table 4a. ac characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at f max unless noted otherwise. note 1: measured from the differential input crossing point to the output at v dd /2. note 2: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the outputs are measured at v dd /2. note 3: this parameter is defined in accordance with jedec standard 65. table 4b. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at f max unless noted otherwise. note 1: measured from the differential input crossing point to the output at v dd /2. note 2: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the outputs are measured at v dd /2. note 3: this parameter is defined in accordance with jedec standard 65. parameter symbol test conditions minimum typical maximum units f max output frequency 350 mhz t pd propagation delay, note 1 ? 350mhz 1.7 2.0 2.3 ns t sk(pp) part-to-part skew; note 2, 3 500 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 100mhz, integration range (637khz ? 10mhz) 0.21 ps t r / t f output rise/fall time 0.8v to 2v 100 250 400 ps odc output duty cycle ? 166mhz 45 50 55 % 166mhz < ? 350mhz 40 50 60 % parameter symbol test conditions minimum typical maximum units f max output frequency 350 mhz t pd propagation delay, note 1 ? 350mhz 1.9 2.2 2.5 ns t sk(pp) part-to-part skew; note 2, 3 500 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 100mhz, integration range (637khz ? 10mhz) 0.21 ps t r / t f output rise/fall time 20% to 80% 250 550 ps odc output duty cycle ? 250mhz 45 50 55 % 250mhz < ? 350mhz 40 50 60 %
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 5 ics83031ami rev. c october 31, 2008 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. offset frequency (hz) ssb phase noise dbc/hz additive phase jitter @ 100mhz 12khz to 20mhz = 0.21ps (typical)
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 6 ics83031ami rev. c october 31, 2008 parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit differential input level 3.3v output rise/fall time 2.5v core/2.5v lvcmos output load ac test circuit part-to-part skew 2.5v output rise/fall time scope qx lvcmos gnd v dd 1.65v0.15v -1.65v0.15v v dd gnd clk nclk v cmr cross points v pp 0.8v 2v 2v 0.8v t r t f q0 scope qx lvcmos gnd v dd 1.25v5% -1.25v5% t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy 20% 80% 80% 20% t r t f q0
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 7 ics83031ami rev. c october 31, 2008 parameter measurement in formation, continued propagation delay output duty cycle/pulse width/period application information wiring the differential input to accept single ended levels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input nclk q0 clk t pd v dd 2 t period t pw t period odc = v dd 2 x 100% t pw q0 v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 8 ics83031ami rev. c october 31, 2008 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. bo th signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 2c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 2b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 2f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 9 ics83031ami rev. c october 31, 2008 reliability information table 5. ja vs. air flow table for an 8 lead soic transistor count the transistor count for ICS83021I is: 416 pin-to-pin compatible with the mc100ept21 package outline and package dimensions package outline - m suffix for 8 lead soic table 6. package dimensions reference document: jedec publication 95, ms-012 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard test boards 123c/w 110c/w 99c/w multi-layer pcb, jedec standard test boards 103c/w 94c/w 89c/w 150 il (n b d ) soic all dimensions in millimeters symbol minimum maximum n 8 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 0 8
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 10 ics83031ami rev. c october 31, 2008 ordering information table 7. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83021ami 83021ami 8 lead soic tube -40 c to 85 c 83021amit 83021ami 8 lead soic 2500 tape & reel -40 c to 85 c 83021amilf 83021ail ?lead-free? 8 lead soic tube -40 c to 85 c 83021amilft 83021ail ?lead-free? 8 lead soic 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applicat ions, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
ICS83021I 1-to-1 differential-to-lvcmos/lvttl translator idt? / ics? lvcmos/lvttl translator 11 ics83031ami rev. c october 31, 2008 revision history sheet rev table page description of change date b t2 t3b t3c t3d t4b 2 3 3 3 4 5 6 7 pin characteristics table - added 2.5v c pd . added 2.5v power supply table. lvcmos table - added 2.5v v oh . differential table - added 2.5v. added 2.5v ac characteristics table. added 2.5v output load ac test circui t diagram, and 2.5v output rise/fall time diagrams. updated figure 1. added differential clock input interface section. 6/3/04 b t4a 2 4 pin characteristics table - changed c in 4pf max. to 4pf typical. 3.3v ac characteristics table - changed odc test conditions. 6/30/04 b t7 1 10 features section - added lead-free bullet. ordering information table - added lead-free part number. 3/21/05 c t4a, t4b t7 1 4 5 11 features section - added additive phase jitter bullet. ac characteristics tables - added additive phase jitter row. added additive phase jitter plot. added lead-free note. 12/12/05 c 1 8 9 pin assignment - corrected package body measurements. updated differential clock input interface. updated reliability information . updated datasheet format . 6/18/08 c t4a, t4b 1 4 corrected typo in header from 1-to-2... to 1-to-1.... ac tables - added temperature note. 10/31/08
ICS83021I 1-to-1 differential-to- lvcmos/lvttl translator www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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